A.2.3 The VXIbus Extensions
VXIbus retains P1 and the center row of P2 exactly as defined by VMEbus. This includes the 5 volt and
±12 volt power pins on P1 and the additional 5 volt pins on P2. VXIbus includes the A and B card sizes and
these modules remain totally VMEbus compatible. However, VXIbus has made substantial additions to the
VMEbus specification oriented towards instrumentation that can best be described as an electromechanical
superset and a logical subset.
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A.2.3.2 VXIbus SUBSYSTEMS
A VXIbus system may have up to 256 devices, including one or more VXIbus subsystems. A VXIbus
subsystem consists of a central timing module referred to as Slot 0 with up to twelve additional instrument
modules. P2 and P3 are completely defined in a VXIbus subsystem. These thirteen modules conveniently fill
a standard 19 inch cabinet when mounted vertically on 1.2 inch centers. Many VXIbus systems will consist
only of a single frame with these thirteen modules. A common configuration will load the Slot 0 module with
system resources such as the VXIbus mandated timing generation, the VMEbus required system controller
functions and a data communication port such as IEEE 488 or RS-232. Slot 0 may also include optional
instrumentation. The other positions are general purpose slots for the user to mix and match modules. A
single VXIbus subsystem may have less than 12 additional slots, but may not have more. Any combination of
VXIbus subsystems may exist within a VXIbus system. For instance, one VXIbus system may consist of a
frame with one Slot 0 and twelve VXIbus modules extended to another frame that has a Slot 0 adjacent to three
instrument slots, another Slot 0 with five instrument slots and four standard VMEbus slots of undefined P2.

A.2.3.2.1 P2 Connector Definition
As mentioned previously, a VXIbus subsystem defines all P2 and P3 pins. The VXIbus P2 adds a 10 MHz
ECL clock, ECL and analog supply voltages, ECL and TTL trigger lines, an analog summing bus, a module
identification line and a daisy chain structure known as the local bus. The trigger lines serve primarily as
resources for signaling between instruments in a VXIbus subsystem, while the local bus lines are preferred for
use within a multiple module instrument set (adjacent slots). The daisy chain local bus use is left to the module
manufacturer to define and several classes of electrical signals are permitted. Allowed signals are TTL, ECL,
low voltage analog and analog up to 42 volts. A keying mechanism near the faceplate indicating that module's
local bus class prevents incompatible classes from accidentally being placed adjacently and potentially causing
a destructive condition. Typical uses of the local bus include creating an internal analog bus or a chain of
serial digital signal processors. There are a total of twenty-four local bus pins on P2, twelve lines in and
twelve lines out for each slot; thus creating a twelve line bus that may or may not be passed on to adjacent
slots.

A.2.3.2.2. P3 Connector Definition
The VXIbus P3 connector adds many of the same resource types as described for P2, but is aimed at higher
performance instrumentation. Included on P3 is a 100 MHz clock and sync signal, additional power pins of the
same supply voltages, more ECL trigger lines and twenty-four additional lines (48 pins) of daisy chain local
bus. Also defined on P3 is a "star" trigger system where precision ECL trigger signals are routed through Slot
0 acting as a cross point switch. This allows very precisely matched trigger timing between modules
regardless of module position.

In order to support automatic system and memory configuration, the VXIbus standard specifies a minimum
amount of capability on each device regardless of its function. A VXIbus device (see Section C.2, "Device
Operation"), being the lowest element of a hierarchy, has a set of "Configuration Registers", all totally
accessible from P1 on VMEbus which allow the system to identify the device, its class, model and
manufacturer, address space (A16, A24, A32, A64) and memory requirements. VXIbus devices with only this
minimum level of capability are called REGISTER BASED DEVICES. 
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VXIbus also defines MEMORY DEVICES, (See Section C.2.3, "Memory Devices") that can be identified as RAM, ROM or other memory types and be configured in contiguous blocks of memory based on speed or memory type.
If a higher level of communication ability between modules is desired in the system, VXIbus defines a class of
devices called MESSAGE BASED DEVICES. In addition to the configuration registers mentioned above,
Message Based Devices are required to have communication registers that are accessible to other modules in
the system. Each device in the system can then use specific communication protocols such as VXIbus's Word
Serial Protocol (See Section C.3.3.1, "Word Serial Protocols") to communicate with other devices. 
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Communication between VXIbus devices is based on a hierarchical device relationship involving
COMMANDERS and SERVANTS. For many systems, such as the single CPU system shown in Figure C.1,
only the first level of this hierarchy exists. In that example, the CPU and host interface device is a Commander which controls the three instrument Servants. A Commander is able to initiate communication with its
Servants based on their capabilities. If the Servants are Message Based Devices, such communication can take
place using COMMANDS which are described by the Word Serial Protocols. Communication with Register
Based Servants is device dependent and may vary between systems. The Commander/Servant hierarchy can
be nested since a Message Based Device may be a Commander as well as a Servant to the next level above it.

C.2.1.1.1 Device Addressing
All VXIbus devices have registers located within 64 byte blocks in the A16 address space. The base address of
a device's registers is determined by the device's unique Logical Address. The Logical Address selector is an
eight (8) bit selector which has 256 unique settings. The Logical Address is the value indicated by this selector
and corresponds to bits 6 →13 of the device register base address. Bits 14 and 15 of the base address are both
1 and the base address is:
     V × 64 + 49152
where V is the device's Logical Address.