Education of Chip Designers at a Large Scale: A Proposal
https://ieeexplore.ieee.org/document/10584365
https://ieeexplore.ieee.org/document/10584365
Exploring logic synthesis with Yosys
https://www.linkedin.com/posts/ashwinrajesh_a-guide-to-logic-synthesis-using-yosys-ugcPost-7221574339165396993-6sN5
56-pages doc: https://drive.google.com/file/d/13ER2Jb7fj6pUIeCzoba837SHPWG-xX-Y/view
https://www.linkedin.com/posts/ashwinrajesh_a-guide-to-logic-synthesis-using-yosys-ugcPost-7221574339165396993-6sN5
56-pages doc: https://drive.google.com/file/d/13ER2Jb7fj6pUIeCzoba837SHPWG-xX-Y/view
Linkedin
As a digital design student, have you ever wondered how the RTL code we write magically gets transformed into circuits? | Ashwin…
As a digital design student, have you ever wondered how the RTL code we write magically gets transformed into circuits?
Have you ever thought how those always blocks were synthesized into gates and LUTs, or even special blocks like BRAM and DSP blocks?
…
Have you ever thought how those always blocks were synthesized into gates and LUTs, or even special blocks like BRAM and DSP blocks?
…
RISC-V Ecosystem Panel | Open Source is Transforming AI and Hardware
https://www.youtube.com/watch?v=hQfmT_LM-zY
https://www.youtube.com/watch?v=hQfmT_LM-zY
YouTube
RISC-V Ecosystem Panel | Open Source is Transforming AI and Hardware
【2024 ANDES RISC-V CON Silicon Valley】
DEEP DIVE INTO AUTOMOTIVE / AI / APPLICATION PROCESSORS AND SECURITY TRENDS
📍About The Event
Recently, RISC-V, with its open, streamlined, and scalable configuration, has become the mainstream solution adopted by leading…
DEEP DIVE INTO AUTOMOTIVE / AI / APPLICATION PROCESSORS AND SECURITY TRENDS
📍About The Event
Recently, RISC-V, with its open, streamlined, and scalable configuration, has become the mainstream solution adopted by leading…
Let it be here. Life lessons from one of the greatest computer scientists.
https://cacm.acm.org/opinion/life-lessons-from-the-first-half-century-of-my-career/
https://cacm.acm.org/opinion/life-lessons-from-the-first-half-century-of-my-career/
Tenstorrent Wormhole Series
Part 1: Physicalities
Part 2: Which disabled rows?
Part 3: NoC propagation delay
Part 4: A touch of Ethernet
Part 5: Taking apart T tiles
Part 6: Vector instruction set
Part 7: Bits of the MatMul
https://tenstorrent.com/vision/community-highlight-tenstorrent-wormhole-series-part-1-physicalities
Part 1: Physicalities
Part 2: Which disabled rows?
Part 3: NoC propagation delay
Part 4: A touch of Ethernet
Part 5: Taking apart T tiles
Part 6: Vector instruction set
Part 7: Bits of the MatMul
https://tenstorrent.com/vision/community-highlight-tenstorrent-wormhole-series-part-1-physicalities
Tenstorrent
Community Highlight: Tenstorrent Wormhole Series Part 1: Physicalities | Tenstorrent
An in depth look at Tenstorrent Wormhole, originally posted on corsix.org
I'm excited to share a sneak peek of our latest work at Intel Corporation —
a groundbreaking approach to Electronic Design Automation (EDA) that integrates intelligent design agents into the engineering workflow.
Our agent, trained on massive datasets from the best of our engineers, provides real-time insights and solutions within the EDA tools, enabling the solving of tasks ranging from simple to complex multi-iteration challenges, making the design process more efficient and innovative.
*This demo utilizes The OpenROAD Project, an open-source EDA tool developed by The Regents of the University of California.
url: https://www.linkedin.com/posts/itai-yeshurun_intel-eda-llm-ugcPost-7267911435886682112-IIhh
a groundbreaking approach to Electronic Design Automation (EDA) that integrates intelligent design agents into the engineering workflow.
Our agent, trained on massive datasets from the best of our engineers, provides real-time insights and solutions within the EDA tools, enabling the solving of tasks ranging from simple to complex multi-iteration challenges, making the design process more efficient and innovative.
*This demo utilizes The OpenROAD Project, an open-source EDA tool developed by The Regents of the University of California.
url: https://www.linkedin.com/posts/itai-yeshurun_intel-eda-llm-ugcPost-7267911435886682112-IIhh
Thx to @cpu_design
Author — Rahul B. at Tenstorrent
"Here’s my list of 5 papers you should read to learn about Out-of-Order Processors!"
#1 The Microarchitecture of Superscalar Processors by James E. Smith and Gurindar S. Sohi
— Touches on every aspect of superscalar processor design and does an excellent job explaining concepts like register renaming, instruction scheduling, and memory operations.
https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=00476078.pdf
#2 The Alpha 21264 Microprocessor by R. E. Kessler
— Explains the instruction fetch, branch prediction, out-of-order execution, instruction retire and exceptions and the internal memory system for the Alpha 21264 processor.
https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=kessler_-_1999_-_the_alpha_21264_microprocessor.pdf
#3 Implementing Precise Interrupts in Pipelined Processors by James E. Smith and Andrew R. Pleszkun
— This paper does a great job at describing and evaluating solutions to the precise interrupt problem in pipelined processors.
https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=00004607.pdf
#4 Checkpoint Repair for Out-of-order Execution Machines by Wen-mei W. Hwu and Yale N. Patt
— Discusses the several properties for the checkpoint repair mechanism to reset the processor state to a known previous state.
https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=p18-hwu.pdf
#5 A case for (partially) TAgged GEometric history length branch prediction by André Seznec and Pierre Michaud
— This paper provides an excellent introduction to TAGE predictors, covering all relevant terminology along with hardware implementation details.
https://www.irisa.fr/caps/people/seznec/JILP-COTTAGE.pdf
Author — Rahul B. at Tenstorrent
"Here’s my list of 5 papers you should read to learn about Out-of-Order Processors!"
#1 The Microarchitecture of Superscalar Processors by James E. Smith and Gurindar S. Sohi
— Touches on every aspect of superscalar processor design and does an excellent job explaining concepts like register renaming, instruction scheduling, and memory operations.
https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=00476078.pdf
#2 The Alpha 21264 Microprocessor by R. E. Kessler
— Explains the instruction fetch, branch prediction, out-of-order execution, instruction retire and exceptions and the internal memory system for the Alpha 21264 processor.
https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=kessler_-_1999_-_the_alpha_21264_microprocessor.pdf
#3 Implementing Precise Interrupts in Pipelined Processors by James E. Smith and Andrew R. Pleszkun
— This paper does a great job at describing and evaluating solutions to the precise interrupt problem in pipelined processors.
https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=00004607.pdf
#4 Checkpoint Repair for Out-of-order Execution Machines by Wen-mei W. Hwu and Yale N. Patt
— Discusses the several properties for the checkpoint repair mechanism to reset the processor state to a known previous state.
https://course.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=p18-hwu.pdf
#5 A case for (partially) TAgged GEometric history length branch prediction by André Seznec and Pierre Michaud
— This paper provides an excellent introduction to TAGE predictors, covering all relevant terminology along with hardware implementation details.
https://www.irisa.fr/caps/people/seznec/JILP-COTTAGE.pdf
A start-up demonstrating LLM Inference on FPGA Altera Agilex 7M vs Nvidia H100
https://www.positron.ai/
looks pretty fantastic. there are probably some nuances and limitations...
https://www.positron.ai/
looks pretty fantastic. there are probably some nuances and limitations...
www.positron.ai
Positron | Generative AI Acceleration
Positron makes purpose-built hardware to accelerate generative AI.
VeloxCon 2025
https://veloxcon.io/
Keynote Panel Hardware Accelerators: The Next 10x for Data Management
https://www.youtube.com/watch?v=0WSuXCM2LV0
https://veloxcon.io/
Keynote Panel Hardware Accelerators: The Next 10x for Data Management
https://www.youtube.com/watch?v=0WSuXCM2LV0
Once again about TPU: Philosophy and Scaling
https://henryhmko.github.io/posts/tpu/tpu.html
https://henryhmko.github.io/posts/tpu/tpu.html